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Steven A. Przybylski

President and Principal Consultant

Verdande Group, Inc.

734-484-3574

sp@verdande.com

Summary

My greatest strengths derive from my thorough understanding of computer systems and semiconductor technologies, my awareness of the market forces that drive the corresponding industries, and, as a result, my appreciation of the interactions between the two industries. My breadth of experience and the variety of analytic tools at my disposal allow me to consider these interactions at a host of different conceptual levels.

I pride myself on my readiness to undertake any task that needs to be done, to learn from others what is required to complete the task, to thoroughly research the area of inquiry, and to accomplish projects successfully and expediently.

 

Areas of Functional Proficiency

 

Areas of Technical Expertise

Professional Experience

9/91 - Present: President and Principal Consultant, Verdande Group, Inc.

I have consulted on general business planning, product strategy, comparative technical analysis and system-level design in the areas of semiconductor memories, computer systems and CPU architecture, and  memory hierarchy design. My clients are predominantly computer system and semiconductor companies. In addition, I offer patent infringement and general litigation support services to legal firms and due diligence analysis to venture capitalists and securities firms. I write on these topics for both trade magazines and academic journals. I have also taught and presented tutorials to both technical and non-technical audiences on a variety of subjects, including DRAMs and DRAM architecture, memory hierarchy design, and computer systems and CPU architecture.

 

1/90 - 8/91: Consulting Assistant Professor, Stanford University.

I designed and taught an advanced graduate level course on cache and memory hierarchy design and supervised students' research activities.

 

7/89 -  9/91: Systems Architect and Chief Scientist, CMOS Systems Group and
                                                 High-End Systems Group, MIPS Computer Systems.
10/84 - 10/85: Computer Architect and Systems Designer, MIPS Computer Systems.

During MIPS' formative years I played a number of different roles within the architecture, processor design and system design groups. These roles frequently involved cross-functional oversight and vendor-liaison roles. I was involved in the development of the MIPS architecture, the R2000 CPU, the M800 system, the RC6280 server and several projects that did not become products.

 

Education

2000    M.B.A., Haas School of Business, University of California, Berkeley, with emphasis on finance and business strategy

1988   Ph.D., Electrical Engineering, Stanford University. Dissertation: Performance-Directed Memory Hierarchy Design

1982   M.S.E.E., Stanford University

1980   B.A.Sc., University of Toronto. Engineering Science Programme, Computer Science Option

Miscellaneous

I have authored or co-authored two books, a book chapter and over 20 journal and conference papers and technical reports on the subjects of DRAM architecture, RISC architecture, CPU design and implementation, IC design methodology and testing, and cache hierarchy design. I am also a co-inventor of three patents in the area of computer system design.

 

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